
`include "mux1x3_defs.v"

`timescale 1ns / 1ps

module mux1x3(
	i_sel,
	i_data0,
	i_data1,
	i_data2,
	o_data
);

parameter DATA_WIDTH = 32;

input [`MUX1X3_SEL_WIDTH-1:0] i_sel;

input [DATA_WIDTH-1:0] i_data0;
input [DATA_WIDTH-1:0] i_data1;
input [DATA_WIDTH-1:0] i_data2;

output [DATA_WIDTH-1:0] o_data;
reg [DATA_WIDTH-1:0] o_data;

always@( i_sel or i_data0 or i_data1 or i_data2 )
begin
	case( i_sel )
		`MUX1X3_SEL_0 : o_data = i_data0;
		`MUX1X3_SEL_1 : o_data = i_data1;
		`MUX1X3_SEL_2 : o_data = i_data2;
		default				: o_data = {DATA_WIDTH{1'bz}};
	endcase
end

endmodule
